The present invention relates to an improvement in CMOS processing technology, whereby a masking step is saved and improved polysilicon patterning is made possible.
Typically, CMOS processing requires at least four masking steps in addition to those used for NMOS processing, which imposes a great economic disadvantage on CMOS technology. The standard NMOS mask sequence is: (1) Moat (2) threshold-voltage ion implant (3) polysilicon (4) second contact (5) metal (6) POR (Protective Overcoat Removal). By contrast, the normal CMOS process requires at least four additional masks, as follows: (1) Tank (2) moat (3) channel stop (to do channel stopping only between N-channel devices) (4) threshold voltage ion implant (5) polysilicon (6) P+ (for low-sheet-resistance source/drain regions for P channel devices) (7) N+ (source/drain regions for N-channel devices) (8) second contact (9) metal (10) POR.
Thus, it is an object of the present invention to provide a more economical process for fabrication of CMOS devices.
It is a further object of the present invention to provide a process for fabrication of CMOS devices which reduces the number of masking steps required.
One possible way to save a masking step in CMOS processing might be to economize on the two separate masks normally required for the P-type and N-type source/drain regions. However, to do this successfully, it is necessary to find ways to obtain good control of both types of source/drain regions.
It is thus a further object of the present invention to provide a method for formation of both P-type and N-type source/drain regions using only one masking step, while retaining good control of the characteristics of the regions formed.
CMOS processes of varying complexity may be used for fabricating different types of devices. For example, the interconnect technology required for a memory array may be quite simple, whereas that required for a random logic structure (e.g., a microprocessor) may be more complex, and require additional patterned levels. Since acceptance of the simplest processes will also imply economic benefits for the more complex processes, a mask-saving scheme should preferably apply to any CMOS process, whether simple or complex.
It is thus a further object of the present invention to provide a mask-reduction scheme which applies to any CMOS process, whether simple or complex.
One difficulty with polysilicon patterning in the CMOS processing prior art has been that excessive levels of dopant greatly degrade the etching characteristics of the polysilicon. In particular, if the polysilicon is doped to have a sheet resistance much below 50 ohms per square, etching tends to occur along grain boundaries, so that fine-line patterning is no longer possible. This problem is acute with present day etching techniques such as chloro-etching (e.g. plasma etching in CCl.sub.4). While it is possible that further etching techniques may be developed to alleviate this problem (e.g. RIE), such texhniques are not now reliably available.
If the polysilicon is to be exposed to the P-type source/drain implant, it must be heavily doped to begin with, with consequent degradation of the etching characteristics, or else the dopant compensation introduced by the P+ source/drain implant will cause the polysilicon to have an unacceptably high sheet resistance.
To avoid exposure of the polysilicon to the P+ source/drain implant, one possibility is to leave the photoresist for the gate patterning step in place. However, this technique, if used in conjunction with prior art source/drain formation techniques, has two major disadvantages: First, the P+ source/drain mask must be spun on over the patterned gate photoresist in place, and the P+ source/drain mask must then be patterned itself. Therefore, if rework on the P+ source/drain mask is necessary, the patterned gate photoresist will also be removed. Since the patterned gate photoresist is self-aligned, it cannot be replaced, and therefore substantial discards will occur in production which could otherwise have been saved by reworking. Second, this technique would appear not to be practical if positive photoresist is used, since dissolution of the exposed P+ source/drain photoresist will also tend to break down the patterned gate photoresist over the gates of P-channel devices. Since positive resists appear to be preferable in the further development of fine-line lithography, this is a serious drawback.
It is thus an object of the present invention to provide a process for forming source/drain regions of either conductivity type in a CMOS structure, which prevents polysilicon regions from being compensated by a source/drain implant.
It is thus a further object of the present invention to provide a process for forming CMOS source/drain regions, which protects polysilicon from being compensated by a source/drain implant, without introducing any non-reworkable steps.
It is a further object of the present invention to provide a process for forming CMOS source/drain regions which permits use of positive photoresists for patterning the polysilicon, and which permits use of only moderately doped polysilicon.